Modern processor system IC chips have a large number of circuits which require a corresponding large number of input/output (I/O) pads for coupling signals from the circuits to other system ICs or devices. Because the wiring density on a system IC is much greater than is possible with printed circuit boards (PCBs) used to interconnect system IC devices and other system components, second level packages are required to fan-out the I/Os to a lower density compatible with the wiring capacity of the PCB. Wiring capacity of a PCB is dictated by the number of lines per channel (between vias) and the number of wiring layers. This requires that the pads on the system IC be coupled to the pads on the second level package with some conductive structure (e.g., wires, tape automated bonding (TAB) traces, solder balls, etc.). Modern system ICs also operate with high frequency I/O driver circuits which require the inductance of the conductive structure to be low so that power connections as well as I/O driver connections have minimum transients caused by the fast changing currents that may occur. For this reason, most system ICs with a large number of high performance circuits use small solder balls to connect to the second level package (module) and likewise use an array of solder balls to connect from the module to the PCB. The array of solder balls is termed “ball grid array” (BGA).
During the design phase of a system IC, it is often necessary to have sockets for the BGA modules housing the system IC so that it may be temporarily coupled to various test fixtures for functional, performance, and failure analysis. Therefore, most system IC manufacturers have invested in test fixtures compatible with the various BGA modules that it uses to package the system ICs that it manufactures. These standard BGAs may come with various numbers of I/Os as well as have a variety of configuration patterns for the solder balls themselves.
Since a multiple processor or even a single processor system IC may have millions of transistors and very complex circuitry, it is often desirable to make test ICs that test a subset of the circuitry. These test ICs have fewer transistors, may be smaller, and would naturally have a requirement for fewer I/Os. Since their I/O count is reduced, many times these test ICs are packaged in different modules. Since the test ICs are not going to be used in a product, their I/O structure is designed for convenience. For added flexibility, the I/Os are typically wire bonded to a second level packaging module. This may be simple and flexible, however, the test modules may no longer be compatible with the test fixtures and the programs used to couple signals to the production level modules. Likewise, if wire bonding is used, signal frequencies may be less than is possible with production level circuits. This may reduce the amount of information about the operation of production level circuits that may be acquired from operating the test ICs.
Therefore, there is a need for a method and apparatus that allows test ICs and their second level packaging modules to more nearly match their production counterparts. This will result in test and debug of test ICs under conditions closer to the conditions that will be experienced by production level system ICs to which they correspond. Also production level test fixtures and programs may be employed when operating the test ICs.